?? shenzhen fuman electronics co., ltd. 54HC164/74hc164 ( ?? s &cic0464) 8 bit ?? 1 ? 7 ? ? and - gated (enable/disable) serial inputs ? fully buffered clock and serial inputs ? direct clear ? package options include plastic small - outline (d) and ceramic flat (w) packages, ceramic chip carriers (fk), and standard plastic (n) and ceramic (j) 300 - mil dips description these 8 - bit shift registers feature and - gated serial inputs and an asynchronous clear (clr) input. the gated serial (a and b) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip - flop to the low level at the next clock (clk) pulse. a high - level input enables the other input, which then determines the state of the first flip - flop. data at the serial inputs can be changed while clk is high or low, provided the minimum set up time requirements are met. clocking occurs on the low - to - high - level transition of clk. the 54HC164 is characterized for operation over the full military temperature range of C 55 to 125 . the 74hc164 is characterized for operation from - 40 to 85 . 54HC164j or w package 54HC164fk package (top view) 74hc164d or n package 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 4-apr-2006 sheet of file: e:\ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b qa qb qc qd gnd clock clear qe qf qg qh vdd 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 4-apr-2006 sheet of file: e:\ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a b qa nc qb nc qc qd gnd nc clk clr qe nc qf nc qg nc-no internal connection qh vcc nc 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 4-apr-2006 sheet of file: e:\ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : function table inputs outputs clr clk a b qa qb...qh l x x x x x x h h h h l l l h h x l l l qa0 qb0 qh0 h l l qan qan qan qgn qgn qgn qa0,qbo,qh0=the level of qa,qb,or qh, respectively,before the indicated steady-state input conditions were established qan,qgn=the level of qa or qg before the most recent transition of clk:indicates a 1-bit shift
?? shenzhen fuman electronics co., ltd. 54HC164/74hc164 ( ?? s &cic0464) 8 bit ?? 2 ? 7 ? logic symbolt ? this symbol is in accordance with ans/ie ee std 91 - 1984 and iec publication 617 - 12. ? pin numbers shown are for the d, j, n, and w packages. logic diagram (positive logic) 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 4-apr-2006 sheet of file: e:\ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : c1/ r srg 8 clr clk a b qa qb qc qd qe qf qg qh 1 2 3 4 5 6 8 9 10 11 12 13 1d & 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 4-apr-2006 sheet of file: e:\ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : c1 1d r c1 1d r c1 1d r c1 1d r c1 1d r c1 1d r c1 1d r c1 1d r clk a b clr 1 2 3 4 5 6 8 9 10 11 12 13 qa qb qc qd qe qf qg qh pin numbers shown are for the d,j,n and w packages.
?? shenzhen fuman electronics co., ltd. 54HC164/74hc164 ( ?? s &cic0464) 8 bit ?? 3 ? 7 ? typical clear, shift, and clear sequence absolute maximum ratings over operating free - air temperature ranget suppl y voltage range, vcc .. - 0.5v to 7v input clamp current, i ik (v i <0 or vi>vcc)(see note 1) 20ma output clamp current, iok (vo<) or vo>vcc)(see note 1) . 20ma continuous output current, io (vo =0 to vcc) 25ma continuous current through vcc or gnd 50ma packaged thermal impedance, ja (see note 2): d packaged .127 /w n package .. 78 /w storage temperature range, ts tg - 65 to 150 t stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyon d those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and out put current ratings are observed. 2. the package thermal impedance is calculated in accordance with jesd 51, except for through - hale packages, which use a trace length of zero. 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 5-apr-2006 sheet of file: e:\ ?? \e \ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : clear clear qh qg qf qe qd qc qb qa clk b a clr serial inputs output
?? shenzhen fuman electronics co., ltd. 54HC164/74hc164 ( ?? s &cic0464) 8 bit ?? 4 ? 7 ? recommended operating conditions 54HC164 74hc164 unit min nom max min nom m ax vcc supply voltage 2 5 6 2 5 6 v ih high - level input voltage vcc=2v 1.5 - - 1.5 - vcc=4.5v 3.15 - - 3.15 - vcc=6v 4.2 - - 4.2 - v il low - level input voltage vcc=2v 0 - 0.5 0 - 0.5 vcc=4.5v 0 - 1.35 0 - 1.35 vcc=6v 0 - 1.8 0 - 1.8 v i input voltage 0 - vcc 0 vcc v v o output voltage 0 - vcc 0 vcc v t tt input transition (rise and fall) time vcc=2v 0 - 1000 0 - 1000 ns vcc=4.5v 0 - 500 0 - 500 vcc=6v 0 - 400 0 - 400 t a operating free - air temperature - 55 - 125 - 40 - 85 t if this device is used in the threshold region (from v il max=0.5v to v ih min=1.5v), there is a potential to go into the wrong state from induced grounding, causing double clocking. operating with the inputs at tt=1000ns and vcc=2v does not damage the d evice; however, functionally, the clk inputs are not ensured while in the shift, count, or toggle operating modes. electrical characteristics over recommended operating free - air temperature range (unless otherwise noted) parameter test conditions vcc t a =25 54HC164 74hc164 unit min typ max min max min max v oh v i =v ih or v il i oh = - 20ua 2v 1.9 1.998 - 1.9 - 1.9 - v 4.5v 4.4 4.499 - 4.4 - 4.4 - 6v 5.9 5.999 - 5.9 - 5.9 - i oh = - 4ma 4.5v 3.98 4.3 - 3.7 - 3.84 - i oh = - 5.2ma 6v 5.48 5.8 - 5.2 - 5.34 - v ol v i =v ih or v il i ol =20ua 2v - 0.002 0.1 - 0.1 - 0.1 v 4.5v - 0.001 0.1 - 0.1 - 0.1 6v - 0.001 0.1 - 0.1 - 0.1 i ol =4ma 4.5v - 0.17 0.26 - 0.4 - 0.33 i ol =5.2ma 6v - 0.15 0.26 - 0.4 - 0.33 i i v i =v cc or 0 6v - 0.1 100 - 1000 - 1000 na i cc v i =v cc or 0, i o =0 6v - - 8 - 160 - 80 ua c i 2v to 6v - 3 10 - 10 - 10 pf
?? shenzhen fuman electronics co., ltd. 54HC164/74hc164 ( ?? s &cic0464) 8 bit ?? 5 ? 7 ? timing requirements over recommended operating free - air temperature range (unless otherwise noted) vcc t a =25 54HC164 74hc164 unit min max min max min max f clock clock frequency 2v 0 6 0 4.2 0 5 mhz 4.5v 0 31 0 21 0 25 6v 0 36 0 25 0 28 t w pulse duration clr low 2v 100 - 150 - 125 - ns 4.5v 20 - 30 - 25 - 6v 17 - 25 - 21 - clk high or low 2v 80 - 120 - 100 - 4.5v 16 - 24 - 20 - 6v 14 - 20 - 18 - t su setup time before clk date 2v 100 - 150 - 125 - ns 4.5v 20 - 30 - 25 - 6v 17 - 25 - 21 - clr inactive 2v 100 - 150 - 125 - 4.5v 20 - 30 - 25 - 6v 17 - 25 - 21 - t h hold time, data after clk 2v 5 - 5 - 5 - ns 4.5v 5 - 5 - 5 - 6v 5 - 5 - 5 - switching characteristics over recommended operating free - air temperature rang, c l =50pf (unless otherwise noted) (see figure 1) parameter from (input) to (output) vcc t a =2 5 54HC164 74hc164 unit min typ max min max min max f max 2v 6 10 - 4.2 - 5 - mhz 4.5v 31 54 - 21 - 25 - 6v 36 62 - 25 - 28 - t phl clr any q 2v - 140 205 - 295 - 255 ns 4.5v - 28 41 - 59 - 51 6v - 24 35 - 51 - 46 t pd clk any q 2v - 115 175 - 265 - 220 4.5v - 23 35 - 53 - 44 6v - 20 30 - 45 - 38 t t 2v - 38 75 - 110 - 95 ns 4.5v - 8 15 - 22 - 19 6v - 6 13 - 19 - 16
?? shenzhen fuman electronics co., ltd. 54HC164/74hc164 ( ?? s &cic0464) 8 bit ?? 6 ? 7 ? operating characteristics, t a =25 parameter test conditions typ unit cpd power dissipat ion capacitance no load 135 pf parameter measurement information notes: a. c l includes probe and test - fixture capacitance. b. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by generators having the following characteristics: prr 1mhz, z o =50 , t r =6ns, t f =6ns. c. for clock inputs, f max is measured when the input duty cycle is 50% d. the outputs are measured one at a time with one input transition per measurement. e. t plh and t phl are the same as t pd . figure 1. loa d circuit and voltage waveforms 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 6-apr-2006 sheet of file: e:\ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : from output under test test point cl=50pf (see note a) load circuit high-level pulse low-level pulse 50% 50% 50% 50% tw vcc vcc 0v 0v voltage wavdforms pulse durations reference input data input 50% 50% 50% 10% 10% 90% 90% tr tf vcc vcc 0v 0v voltage waveforms setup and hold and input rise and fall times input in-phase output out-of-phase output 50% 50% 50% 50% 50% 50% 10% 10% 10% 10% 90% 90% 90% 90% tplh tplh tphl tphl tf tr vol vol voh voh 0v vcc voltage waveforms propagation delay and output transition times
?? shenzhen fuman electronics co., ltd. 54HC164/74hc164 ( ?? s &cic0464) 8 bit ?? 7 ? 7 ? pad assignment pad no pad name x y 1 a - 242.00 - 53.50 2 b - 250.00 252.00 3 qa - 135.00 - 188.50 4 qb 0.00 - 188.50 5 qc 115.00 - 188.50 6 qd 252.00 - 188.50 7 gnd 252.00 - 73.50 8 clock 241.85 41.50 9 clear 252. 00 180.50 10 qe 137.00 190.50 11 qf 2.00 190.50 12 qg - 113.00 190.50 13 qh - 250.00 190.50 14 vdd - 250.00 61.50 ? 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 6-apr-2006 sheet of file: e:\ \ ? \ ? -0\zbo\54HC164(74hc164).ddb drawn by : a b qa qb qc qd gnd clock clear qe qf qg qh vdd 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a title number revision size b date: 19-may -2006 sheet of file: c:\documents and settings\user\ \520.ddb drawn by : vdd qh qg qf qe clr clock gnd qd qc qb qa b a + vdd 1k 104p 47uf 10k cpu 74hc164 *???cpu? ??
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